Memory devices are becoming faster. Input/output (I/O) circuits in memory devices, and I/O circuits that communicate with memory devices, should be fast enough to support the speed of memory devices. Skew (variations in phase) between individual bits within an interface is one problem that threatens to keep I/O circuits from supporting the ever-increasing speeds of memory devices.
Skew has typically been managed by closely matching the layout of integrated circuits and printed circuit boards to reduce the skew between all data signal traces coupled to a single memory device. Any remaining skew between the data signals and a received clock signal is then managed by de-skewing the clock relative to all of the data signals as a group.